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    Two-Dimensional Layered Materials for Nanoelectronics

    Editor:xtt Date:2018-05-25 Hits:100

     

    TimeMay  25,  201814:30-15:30

     

    Place : Room 31811th teaching building Yuquan Campus

     

    TitleTwo-Dimensional Layered Materials for Nanoelectronics

     

    SpeakerYang ChaiDepartment of Applied Physics, The Hong Kong Polytechnic University

     

    E-mail: ychai@polyu.edu.hk

     

    Abstract As the Moore’s law is coming close to its end, the development of future semiconductor research requires low power and high performance nanoelectronics (More Moore) and diverse and multifunctional devices (More than Moore). It has been becoming inevitable to introduce new materials into the existing Si platform to augment its functions. Two-dimensional (2D) layered semiconductors possess ultrathin body, atomic scale smoothness, dangling bond-free surface, reasonable good mobility, and sizable bandgap. Recently, we used graphene as the barrier of the Cu interconnect to replace conventional TaN barrier. Our experimental and computational results show that graphene barrier can meet the ITRS requirement. We also reveal distinct growth dynamics of semiconducting MoS2 flakes using in-situ transmission electron microscopy, and demonstrate a systematic study on group-10 transition metal dichalocogenides.

     

    BioDr. Yang Chai received his PhD degree from the Hong Kong University of Science and Technology in 2009. After he conducted his Postdoctoral studies at Stanford University and University of Illinois at Urbana & Champaign, he joined the Department of Applied Physics in the Hong Kong Polytechnic University in 2012 as an Assistant Professor. He is a recipient of RGC Early Career Award in 2014, the IEEE Distinguished Lecturer since 2016, and the Semiconductor Science and Technology Early Career Research Award in 2017. His current research interest includes low-dimensional material for electron devices and energy devices.